012How much memory can each AI chip get?

What the balance says

How we count. Supply is HBM wafer starts times the good terabytes each wafer yields. Demand is units times HBM per package, bought about four months before the accelerator ships, plus about 6% for stacks lost in 2.5D assembly and physical capacity above the usable figure. The lead matters when growth is steep: purchases run 37% above the bits inside 2026’s shipments, because 2027’s step-up is bought early, and 13–17% above in 2027–30.

2026 is roughly balanced (−2%). That fits the price signal: HBM contract prices paused or slipped in 2026 while commodity DRAM rose about sixfold. In 2025, supply (about 2.8 EB) ran well ahead of the bits shipped inside accelerators. The excess went into inventory across the chain: Nvidia’s own rose from about $10B to $21B over its fiscal 2026 and reached $31.6B by July 2026.

2027 is the crunch at announced specs. Demand jumps with TPU 8, Trainium 3–4, MI450, MTIA and the first Rubin Ultra builds. Supply grows only 54%: wafer input rises 31% and good bits per wafer 18%, less than node shrinks alone would give because the HBM4 die is larger for its doubled interface. The announced specs would need 7.3 EB against about 6.0 EB available.

2028–30 turns on two things we can’t know yet: how fast memory per package grows again, and how many packages the power grid can absorb. New cleanrooms lift supply 33% in 2028 and about 24% a year after. If memory per package grows about 17% a year, the market stays balanced; if it follows the announced roadmaps, supply falls more than a third short.

How this compares with published views

Supply ÷ demand − 1. Goldman sits between our two cases; J.P. Morgan’s deeper −16% came in September, after the first trims were reported.

The commodity DRAM squeeze is the same story one step removed. With nearly every new big-three wafer going to HBM, conventional bit growth has to come from node shrinks and CXMT. AI then takes a second bite through CPU memory: Vera’s LPDDR5X, AMD Helios’s 36 TB of DDR5 per rack, and agentic CPU servers. Counting HBM at its wafer cost, AI systems take roughly 27% of DRAM wafers in 2026 and about 43% in 2027, by our estimate from the rack configurations below. Conventional contract prices compounded roughly sixfold from 3Q25 to 4Q26, with 4Q26 still up 10–15% (TrendForce). IDC expects 2026 PC shipments to fall 11.3% and smartphones 13%. Published 2027 DRAM sufficiency ranges from −1.9% (DS Investment) to −5.9% (Goldman); Micron calls 2027–28 “tighter than 2026”.

Is Nvidia really cutting memory per GPU?

Partly. No shipping data-center GPU has lost HBM: Rubin keeps 288 GB, the same as Blackwell Ultra. But Nvidia is reported to be halving Vera’s CPU memory for 2027 builds and cutting Rubin Ultra’s HBM by 75–81% per package against its announced spec. HBM per GPU has stopped growing this generation, and per compute die it is set to fall in the next.

Per compute die, the cut is real. Rubin carries 144 GB per die; the reported Rubin Ultra carries 96 GB per die, a third less, against 256 GB per die in the original plan. Half of the package-level drop comes from going from four dies to two, which sources put down to packaging and rack issues rather than memory.

It is not just Nvidia. AMD reportedly built a 288 GB MI450 for Meta beside the 432 GB MI455X. TrendForce says GPU and ASIC makers are “considering reducing HBM capacity per device” and will evaluate 8-Hi stacks in 2027. The tell: 8-Hi stacks now carry a 10–30% per-gigabit premium over 12-Hi, the reverse of normal pricing.

Why. SemiAnalysis gives three reasons for Rubin Ultra. There are not enough HBM wafers to build 12-Hi stacks for the logic and CoWoS capacity Nvidia has secured for 2027, and 8-Hi yields more stacks per wafer. HBM cost jumps in 2027: GF Securities estimates memory would have reached about 29% of a Vera Rubin system’s bill of materials without the Vera cut, against Nvidia’s preferred 20%. And workloads are shifting: a 576-GPU domain of 192 GB parts (about 110 TB) still dwarfs a 20.7 TB NVL72.

Nvidia has guided its gross margin down from 75% to 71–72% by the quarter ending January 2027 on “extreme pricing conditions in memory”. Its supply and capacity purchase commitments, mainly memory, rose from $119B to $279B in one quarter. The logic is to protect units by trimming memory per unit: TrendForce describes the Vera cut as “lowering memory per module while increasing total module shipments”, a supply-driven compromise, not a drop in demand. We model the reported trims as the base case and the announced specs as the alternative.

How much memory per accelerator the market can afford

To balance, fleet-average HBM per accelerator can be about 270 GB in 2027, 320 GB in 2028 and 430 GB in 2030: growth of about 17% a year, against 28% on the announced roadmaps. That is feasible. 288 GB stays the flagship through 2027, next-generation parts move to 8-Hi stacks, and capacity beyond that moves off HBM. It is a fleet average, so a 432 GB part has to be offset by a 144–216 GB part elsewhere.

• 2027 (~270 GB). Rubin, TPU 8i and the 288 GB MI450 sit at the top of the affordable range. The 432 GB MI455X and the 384–512 GB MTIA 500 fit only if Trainium 3 (144 GB), TPU 8t (216 GB) and Maia 200 (216 GB) keep the average down.
• 2028 (~320 GB). Rubin Ultra at 192–256 GB on two dies fits. The announced four-die, 1 TB version would absorb about a fifth of 2028 supply on about 15% of units.
• 2029–30 (~380–430 GB). Room returns for Feynman-class parts at 400–600 GB, as long as custom ASICs stay near 300–420 GB.

Per compute die, that means about 100–130 GB on Rubin Ultra (Rubin: 144 GB) and roughly 200 GB per die by 2030.

Workloads can live with it. MLPerf Inference v6.1 compares GB300 (278 GB) with GB200 (186 GB) at the same 8 TB/s. A 671B model and small models that can’t be capacity-bound gained the same ~1.29×, so the gain from capacity itself was about zero. Our modelling of a one-third cut, 288 GB to 192 GB through 8-Hi stacks at unchanged bandwidth:

• 0–10% throughput loss for today’s dominant pattern: 0.7–2T-parameter MoE models on 72 or more GPUs with wide expert parallelism, 32K–400K context. Weights take about 20–45 GB per GPU at that width, depending on precision and replication; the rest is KV cache.
• 15–30% loss for 10T-class models, sparse-attention long-context agents, or idle sessions parked in HBM. About 45% in the worst combination.
• 0–12% for training.
• Concurrency falls more than throughput. Sessions per GPU drop 36–41%, because weights are a fixed charge, but per-user decode speeds up, so tokens per GPU fall only 5–11%. Token-priced services barely notice; session-priced agent hosting does, unless KV moves to another tier.

The hard floor is about 155 GB per GPU, below which a 10T-parameter model at FP8 no longer fits in a 72-GPU domain (about 90 GB at FP4). These figures assume FP4 weights, FP8-or-smaller KV cache and an off-HBM KV tier, all shipping on Blackwell and Rubin.

The economics push the same way. At 2027 HBM4 prices of $32–40/GB, 288 GB costs about $9–12K per package and 1 TB about $33–41K. Morgan Stanley puts memory at 25–30% of a Vera Rubin rack’s cost, up from 5–10% in earlier racks. A 12-Hi to 8-Hi switch cuts bits per GPU by a third; with 8-Hi’s 10–30% per-Gb premium, HBM spend per GPU falls 13–27%.

The technology is not the limit; wafers are. Per-stack bandwidth depends on interface width and pin speed, not height, so a shorter stack keeps bandwidth: B200 to B300 proved the inverse, 192 GB to 288 GB on the same eight stacks at 8 TB/s. Packaging allows far more than the market can feed: 12 stacks × 48 GB = 576 GB in 2027, and 20 × 64 GB ≈ 1.3 TB by 2028–29 on TSMC’s roadmap.

Demand: units, memory per unit, and each generation’s appetite

Accelerator shipments roughly double from about 14M packages in 2026 to 26.5M in 2030 in our base case, and custom ASICs (TPU, Trainium, MTIA, OpenAI’s chip) make up about 60% of units from 2027. At announced specs, the HBM inside each year’s shipments would grow sixfold, from 2.9 EB in 2026 to about 17.5 EB in 2030; at the specs now shipping or reported, about fourfold, to 11.1 EB.

Units. Our 2026–27 paths follow vendor-level evidence: Nvidia’s guide for about 70% revenue growth in its fiscal 2028 (February 2027 to January 2028) at a much higher price per package (a Vera Rubin rack costs roughly twice a GB300 rack), Morgan Stanley’s 2027 CoWoS demand (2.7M wafers, Nvidia about 45%), TPU forecasts of 5–8.8M in 2027, and the AMD, Broadcom and Anthropic deal books. After 2027 units grow 12% in 2028 and about 8% a year after. A capex- and power-constrained top-down view gives far fewer, about 15–17M packages a year through 2030; it is our low case. Pack 010 shows why it matters: see “How this squares with pack 010” below.

Nvidia generations: memory per package, per rack, and over each generation’s life

Lifetime totals use our unit mix (Hopper 5.2M, Blackwell 3.3M, Blackwell Ultra 6.4M, Rubin 8.9M and Rubin Ultra 5.7M packages) and are rounded. Rubin Ultra counts as two-die equivalents.

The Rubin row is the one to notice. Its LPDDR5X attach, even at the reported halved level, matches or exceeds its HBM in bytes, which is why the Vera cut matters for commodity DRAM.

Everyone else’s current parts

By HBM bits, the 2027 split is about 37% Nvidia, 31% Google, 13% AWS, 9% AMD and 9% other ASICs in our base case, close to Morgan Stanley’s 37/36/12% for Nvidia, Google and AMD.

Supply: where the HBM bits come from

HBM output roughly doubles in two years, from about 3.9 EB in 2026 to 6.0 EB in 2027 and 8.0 EB in 2028 in our base case, but only by taking about 30% of the big three’s DRAM wafers. Apart from SK hynix’s M15X and Samsung’s P4 phase 2, both producing since the first half of 2026, no new fab adds volume before mid-2027.

HBM eats wafers more than twice as fast as it makes bits. HBM takes 18%, 22% (vendor capacity figures imply about 25%) and 30% of the big three’s DRAM wafer starts in 2025, 2026 and 2027, but yields only 8%, 9% and 13% of DRAM bits (TrendForce). Micron puts HBM3E at about 3× the wafer area per bit of DDR5 and says the ratio rises each generation. We estimate 650–850 good GB per HBM wafer start in 2026, about twenty 36 GB stacks. The consequence: non-HBM wafer starts at Samsung, SK hynix and Micron stay roughly flat at 1.26–1.33M a month through 2027. Nearly every new wafer goes to HBM.

Capacity by vendor, thousand HBM wafer starts a month

Q2 2026 HBM revenue share: SK hynix 50%, Samsung 33%, Micron 18% (Counterpoint).

From wafers to bits. Our base case runs average HBM wafer input from about 450k a month in 2026 to 590k in 2027, 710k in 2028 and 975k in 2030, with good output per wafer rising from 0.72 TB to 1.05 TB as the industry moves to 1c/1d nodes and 32 Gb dies. That lands close to the published anchors, 1.5 EB in 2024 and about 3.0 EB in 2025 (TrendForce), about 4 EB in 2026, and TrendForce’s +50–60% for 2027: we get 1.5, 2.8 and 3.9 EB and +54%.

Beyond 2027 no vendor publishes HBM capacity. Our 2028–30 path assumes HBM keeps about a third of a big-three DRAM base growing toward about 3M wafer starts a month by 2030 (Citrini puts Samsung and SK hynix alone at 2.3–2.6M). The low and high cases sit about 19% below and 23% above the base in 2028, and 28% below and 33% above in 2030.

Price is what forces the shift. 2026 was an HBM pricing pause: HBM3E sold near $1.50/Gb (about $12/GB) while conventional contract prices compounded about sixfold from 3Q25 to 4Q26, to roughly $2/Gb. By Q1 2026 a wafer of 64 GB server DIMMs earned more than a wafer of HBM. At a 3× wafer ratio, a $2/Gb commodity bit implies about $6/Gb for an HBM bit to break even per wafer. That is why 2027 HBM4 quotes sit at $4–5/Gb (about $32–40/GB, or $1,150–1,450 per 36 GB stack) and blended 2027 forecasts run from +54% (J.P. Morgan) to +121% (TrendForce). The HBM price is now hostage to the commodity price.

Most of it is already sold. Micron has $32B of customer commitments and has contracted the “vast majority” of its 2027 HBM. Samsung has signed five-year agreements with its top five data-center customers and plans to cover 60–70% of capacity; SK hynix has long-term deals with about ten customers. A buyer without a contract in 2027 has very little to buy.

KV cache: the demand driver and the levers

KV cache is what now fills HBM, and it is the most movable part of memory demand. In a typical 2026 serving setup KV takes about 60% of a 288 GB GPU and weights about 15% (LMSYS). Attention design changes KV per token by more than 50× and precision by up to 3.5×, and warm context can be parked in LPDDR, CXL memory or flash. Net: KV growth raises total memory demand but pushes the marginal byte off HBM.

Sizing. KV per token is 2 × layers × KV heads × head size × bytes for standard attention; latent, compressed and linear-attention designs cut it further. At FP8, a 128K-token context ranges from 34 GB on Llama 3.1 405B to 0.7 GB on DeepSeek-V4-Pro, a model four times larger. FP4 KV fits 1.78× more than FP8 but is still experimental, costing 1.6 points on SWE-bench Verified in one test.

Why it keeps growing. Google processed more than 3.2 quadrillion tokens a month in May 2026, against 480 trillion a year earlier. Agents make prompts long and repetitive: 94–98% of coding-agent prompt tokens are reused prefixes, and inputs outnumber outputs 131 to 1. DeepSeek-V4-Pro agent inputs run at a median of 88K tokens and 675K at the 99th percentile; Nvidia sizes Rubin for 128K–400K cached tokens per user.

Where it can live. The tier ladder runs from HBM (the active batch) to CPU LPDDR, optical and CXL pools, flash and network storage (table below). Tiering is now standard in vLLM, SGLang, TensorRT-LLM and Nvidia’s Dynamo. On coding-agent traces, a shared KV store lifted throughput 3.8× and cut time-to-first-token 46× by raising cache hits from 2% to 92%.

• CPU LPDDR. Vera carries 768 GB–1.5 TB per two GPUs over a 1.8 TB/s link. This is Nvidia’s main answer, and why the reported LPDDR cut matters.
• CXL pools. Samsung’s CMM-D pool ran KV offload at about 92% of local-DRAM throughput at TP=8; Alibaba’s CXL pool cut time-to-first-token about 90% against an RDMA store.
• Flash. Nvidia’s BlueField-4 context-memory tier is due in 2H 2026 with “petabytes” per pod and a claimed 5× tokens/s, still unmeasured in public. Citi estimates about 16 TB of NAND per Rubin GPU, about 115 EB in 2027 or 9% of global NAND.
• High Bandwidth Flash. A 512 GB-per-stack design, samples in 2027 and volume in 2028 per analysts, for read-mostly weights, not active KV.

Shrinking it. DeepSeek-V4 stores 8.7× less KV than V3.2 at 1M tokens, Kimi K3 and Qwen3.8 cut per-token KV 2–3× against their predecessors, and Nvidia credits part of GB300’s 1.6× software gain in MLPerf to lower KV precision. Hardware moves the same way: Groq 3 LPX racks run MoE decode from SRAM (500 MB per chip, 128 GB per rack, no HBM) while Rubin GPUs keep attention and KV. The GDDR7-based Rubin CPX no longer appears on Nvidia’s Vera Rubin page.

What it does to the balance. HBM capacity sets concurrency: GB300’s 1.5× HBM over GB200 gave 1.6× the decode batch, and a third less HBM removes 36–41% of resident sequences because weights are a fixed charge. Whether that costs tokens depends on reads. With dense attention, per-user decode speeds up and tokens per GPU fall only 5–11%; with sparse attention, or agent sessions parked between tool calls, the loss approaches the full 40%. Hence the design now shipping: size HBM for the active batch and stage warm context one tier down during tool-call pauses, which last about 5 seconds at the median.

Which tier depends on attention design. At 57 agents per GPU (Artificial Analysis’s measured rate for DeepSeek-V4-Pro on GB300) and 90th-percentile agentic context, an MLA model spills about 25 TB of warm KV per Rubin rack, which fits Vera’s LPDDR. A dense 405B-class model spills 80–280 TB, which needs flash, while DeepSeek-V4-class models fit in HBM (our estimates). So KV growth lands mostly in LPDDR, tightening commodity DRAM, and in NAND: enterprise SSD is now about 37% of NAND demand (CFM), and Citi sees a 6.1% NAND shortfall in 2027.

Our trimmed-spec case assumes that tiering works. If agent hosting is priced per session and insists on HBM-resident context, buyers will pay for taller stacks again, and demand moves toward the announced-roadmap case.

Marvell’s Photonic Fabric and pooled memory

Optical pooling slows the growth of HBM per GPU from 2028; it does not cut it before then. On an accelerator designed around a pool, it could replace 10–20% of HBM capacity in 2028 and 25–35% by 2030. Across the whole fleet that is about 2% in 2028 and 3–8% in 2030 (our estimates).

What Marvell bought. Marvell closed its $3.25B purchase of Celestial AI on February 2, with up to $2.25B more tied to revenue. Photonic Fabric links chips over light at about 2.4–3.1 pJ/bit and adds roughly 200–300 ns of latency; on-package HBM is under 100 ns. The memory module fronts 2 TB of DDR5 with two HBM3E stacks (72 GB) acting as a cache. A 2U appliance of 8–16 modules holds about 33 TB, shared by up to 16 servers as far as 50 m away.

Where it stands. The memory module taped out in 2026, is in bring-up, and samples to “multiple customers” in 2027. Every disclosed win so far is optical interconnect, not pooled memory: a Tier 1 hyperscaler’s XPU scale-up network and co-packaged optics added to the AWS agreement. Marvell’s revenue targets, a $500M run-rate by November 2027–January 2028 and $1B by November 2028–January 2029, are interconnect too. Amazon holds a warrant for 1,045,171 Marvell shares at $87.00 that vests with its Photonic Fabric purchases through 2030, the clearest signal of who adopts first.

It replaces capacity, not bandwidth. The appliance switch moves about 115 Tbps (about 14 TB/s), roughly one Rubin GPU’s HBM4 bandwidth. Shared across 64–128 accelerators, that is 0.1–0.2 TB/s each, about 1% of Rubin’s 19–22 TB/s, while offering 250–500 GB of capacity each. So the pool can hold only bytes touched rarely: warm or parked KV cache, cold MoE experts and adapters, optimizer state, checkpoints. KV for sequences in the active decode batch, and hot weights, are read every token step and stay in HBM.

The lever it unlocks is stack height. HBM capacity comes bundled with bandwidth: drop a stack and you lose both. Shortening stacks keeps bandwidth (12-Hi to 8-Hi cuts GB by a third, 16-Hi to 12-Hi by a quarter), and a pooled tier is what lets a designer take that cut. That bounds displacement near 25–35% per accelerator.

Who adopts, and why the effect is muted. Nvidia, the largest HBM buyer, is building its own non-optical tiers (Vera LPDDR5X, ICMS, the Enfabrica team it paid over $900M for) while its announced Rubin Ultra still lists 1 TB of HBM per package (reportedly cut to 192–256 GB). That leaves custom accelerators (AWS, Google, Meta, Microsoft) and UALink systems as the early market; optical NVLink for Feynman in 2028 is reported but unconfirmed. Vendors sell pooling as a 2–5× throughput gain, mostly from simulation, not as HBM savings, and cheaper tokens can raise total HBM demand, so the industry-level effect is smaller than the per-accelerator one and could be zero. The tell that this is changing would be a named memory-appliance customer or purchase order; none has been disclosed.

China: CXMT, YMTC, Huawei and export controls

China narrows the global commodity DRAM shortfall but barely touches the HBM balance. Hanwha estimates CXMT shrinks the 2026 global DRAM deficit from 15.5% to 9.4%, and 2027’s from 12.0% to 5.6%. Almost none of that reaches HBM, and most of it stays inside China.

CXMT is big in wafers, smaller in bits, and not cheap. It runs about 300–320k wafer starts a month across two Hefei fabs and one in Beijing, heading to about 420k in 2027 and 500–600k in 2028. That is about 17% of the top five makers’ wafer starts but only 6.7–9% of bits, because its nodes lag; it took 9.5% of DRAM revenue in Q2 2026, fourth globally. It prices at parity with Samsung, earned a net margin of about 52% in the first half of 2026 (RMB77.6bn on RMB150.3bn of revenue), and is booked through 2027. Its July STAR Market IPO raised RMB57.9bn ($8.6B). So it relieves volume, not price.

It mostly displaces imports. Goldman puts CXMT at 41% of China’s DRAM demand in 2026 and about 50% by 2028. The bits that frees for Korean and US vendors elsewhere are small next to industry bit growth of 22–24% a year, and Korean HBM conversion is driven by HBM demand regardless.

China’s HBM is a closed, starved loop. CXMT makes HBM3 8-high at about 25% overall yield (SemiAnalysis, June) and began small-scale HBM3E in September; it has no HBM4. Huawei’s pre-control stockpile of about 13M stacks (11.4M from Samsung) runs out in 2026. Epoch AI’s model has about 1.5M Ascend chips in 2026, but only about 240k with domestic HBM, about 30–35M GB or 0.03 EB, while about 750k use non-HBM memory. Ascend prices rose 20–50% in two months; the 950DT now lists above RMB250k. DeepSeek’s order for 160k 950DTs alone would take about 70% of 2026’s domestic HBM.

Export controls cap China’s demand on the Korean and US balance. The December 2024 rule bars HBM above 2 GB/s/mm² of bandwidth density; equipment controls cover every CXMT node. Nvidia’s H200 is licensed, with 25% to the US Treasury and at most 75k units per buyer, but Beijing’s own gatekeeping held deliveries to about 20k by August against more than 2M ordered. Even the full licensed ceiling, about 750k H200s at 141 GB, is about 0.1 EB. China’s draw on Korean and US HBM is policy-gated, small, and could swing either way.

The Korean fabs in China are frozen at their nodes. Samsung’s and SK hynix’s China fabs lost fast-track (validated end-user) status on December 31, 2025 and run on annual licences that bar upgrades. Wuxi is about half of SK hynix’s DRAM capacity, so its HBM growth has to come from Korea and the US while Wuxi drifts toward commodity output that competes with CXMT.

YMTC matters more for flash than DRAM. It is now third in NAND by shipments, with 14–16.5%. Omdia has it adding about 486k NAND wafers in 2027 against about 75k each for Samsung and SK hynix, useful for the SSD tier that holds offloaded KV cache. Its DRAM entry, about 50k wafers, is immaterial before 2028.

Oversupply risk: low through 2027, rising after. China’s DRAM capacity could reach about 1.4M wafer starts a month by 2030, and domestic DUV scanners arrive in 2027–28 (Citrini). An AI air pocket would hit DDR5 and LPDDR5X first, CXMT’s core products. Citrini still models a global DRAM deficit of about 25% in 2030.

Dates to watch. The US affiliates rule returns on November 10 unless extended; the HBM temporary licence expires on December 31; the Korean fabs in China need 2027 licences; and CXMT’s Entity List designation is approved but unpublished.

Terafab and other new capacity

Terafab adds essentially no memory before 2030; through this forecast it matters as a buyer, not a supplier. Our base case puts its DRAM output at about 10,000 wafer starts a month in 2030, roughly 0.1% of global DRAM bits, and no HBM.

What is actually committed. Musk floated a “Tesla TeraFab” in November 2025, described it in January 2026 as “logic, memory and packaging”, and launched it on March 21 with talk of 100,000 wafer starts a month initially and 1,000,000 eventually. Intel joined in April, and the first full-scale phase is to run Intel’s 14A logic process. Two things are firm. A research fab at Giga Texas of “a few thousand” wafers a month, about $3B, starts operating in the first half of 2027; its first test chip is SRAM, due in May–June 2027. And a $16.8B Phase 1 at Grimes County runs from December 1, 2026 to the end of 2028, within up to $119B of phases through 2036. On October 20 Musk targeted volume logic production for Q3–Q4 2028, “with big error bars”. No DRAM capacity, node, process licensor or memory partner has been disclosed; the memory evidence is job postings since August for sub-20nm DRAM process integration and HBM/LPDDR interface design.

Why memory comes late. Incumbents with their own process take about 3.7 years from groundbreaking to first DRAM wafers: Micron’s Idaho ID1 broke ground in October 2023 and outputs first wafers in mid-2027, with meaningful output in 2028. CXMT, the last new entrant, took about 3.5 years to first low-volume output and 8–10 years to a mid-single-digit share. Phase 1’s $16.8B buys roughly one memory fab ($15–20B) or half a leading-edge logic fab, and it is going to logic. Without a licensed DRAM process, first product wafers point to about 2030; HBM, which needs best-in-class DRAM yields plus stacking, comes after that.

Our scenarios. Base (35%): about 2,000 DRAM wafer starts a month in 2029 and about 10,000 in 2030, about 0.1% of 2030 DRAM bits. High (10%), with a licensor signed and tools ordered by mid-2027: about 20,000 and 50,000, about 1% of bits and under 1% of HBM. Low (55%): engineering lots only. For scale, CXMT alone adds about 100,000 wafer starts a month in 2027, twice the high case for 2030.

Net effect: neutral to tighter. Whatever Terafab makes is captive, so it displaces Tesla and SpaceX purchases rather than adding merchant supply. Meanwhile Musk’s companies plan about 13 GW of compute by end-2027, including a 440,000-GPU Vera Rubin cluster by mid-2027, roughly 0.13 EB of HBM4 on its own. Musk himself calls memory “the biggest constraint”. The one real effect before 2030 is on bargaining: a credible in-house threat can weigh on 2028–30 contract pricing before any bits exist.

Other new capacity is incumbents, financed by customers. Outside China there is no new DRAM producer before 2030. SoftBank and Intel’s Saimemory plans Z-Angle Memory prototypes by March 2028 and commercialization in its fiscal 2029, with no capacity disclosed. Buyer money instead funds incumbents’ cleanrooms. Micron has 26 strategic customer agreements covering more than 35% of revenue through 2030, and $32B of customer commitments, mostly prepayments. SK hynix is moving to 3–5-year contracts with 10–30% upfront.

Reading the scenarios

The base case sits on a knife-edge. Moving to the low or high supply case (about −19% or +23%), or ±15% on memory per package, swings 2028 anywhere from 10–17% short to 21–27% long. Three variables decide the cycle: total unit volumes, which power limits; good bits per HBM wafer (HBM4/4E yields, Samsung’s ramp); and whether 8-Hi stacks stick.

Reading the camps. The “oversupply by 2028” view (Bloomberg Intelligence, DS Investment, Morgan Stanley’s Micron model with fiscal 2029 EPS down about 40%) needs either the power-limited build or the supply upside. The “short through 2030” view (SK hynix, Micron, Citrini’s 25% DRAM deficit in 2030) needs the announced roadmaps or the deal books. Our base is neither: within ±3% every year, and only because memory per package stops compounding at its old rate.

How this squares with pack 010. Pack 010 found that from 2027 power and money, not chips, limit what gets switched on: about 38 GW of all-in capacity in 2027, rising to 51 GW in 2030, while the chipmakers could deliver chips for 47–80 GW. On pack 010’s basis (a data center draws about twice its chips’ rated power) and our estimate of 1.4–1.7 kW of chip power per package, our base units need about 55 GW in 2027 and 68–93 GW a year in 2028–30, 7–17% more than pack 010’s chip path. Its switched-on path sits below even our low unit case (41–61 GW). In that low case HBM runs 37–52% long at trimmed specs in 2027–30, and the industry could afford the announced roadmaps instead: supply would sit within −6% to +15% of demand. If chip purchases fall to pack 010’s switched-on path, the surplus is larger still.

Asymmetry. Our base needs more new AI capacity a year after 2027 than pack 010 expects to be switched on, so the unit risk leans down. The downside case for memory makers, a power-limited build with trimmed specs (+52% in 2028), arrives just as Yongin, P5, ID2 and Hiroshima add wafers. The upside needs the announced roadmaps or deal-book volumes, either of which leaves 2028 22–29% short.

What to watch

The next six months settle more of this than the last six: 2027 HBM4 contract prices, whether 8-Hi sticks on Rubin Ultra and the 2027 ASICs, and how many gigawatts actually get switched on. 2027 memory earnings are largely contracted; the open question is 2028.

HBM makers (SK hynix, Samsung, Micron). Pricing power peaks in 2027, when HBM must reprice toward commodity-DRAM parity at about 3× the wafer cost per bit. Micron’s $32B of customer commitments and Samsung’s five-year agreements, planned to cover 60–70% of capacity, make 2027 visible; the equities already discount a 2028 turn (SK hynix about 57% off its June peak, at about 2.7× 2027 earnings per BofA). Our base case says the 2028 risk comes from the demand side, trimmed specs plus a power-limited build, more than from new fabs.

Nvidia. Memory is the main gross-margin headwind (75% to 71–72%) and the reason for server price increases of more than 15%. Trimming memory per GPU protects unit volume; per-die HBM falls on Rubin Ultra.

Custom-ASIC chains (Broadcom, MediaTek, Alchip, Marvell). They take most of 2027’s unit growth and are still mostly on HBM3E, which keeps HBM3E tight through 2027.

Capacity tiers. LPDDR/SOCAMM suppliers, enterprise SSD and NAND, and CXL silicon (Astera Labs, Marvell, Montage) are where KV-cache growth shows up first. Optical pooling (Marvell) and High Bandwidth Flash (SanDisk, SK hynix) come in 2028 and later.

China and Terafab. CXMT relieves volume, not price, and stays mostly domestic; China’s demand for Korean and US HBM is set by policy, not need. Terafab is a buyer through 2030, with bargaining value before it has any bits.